Interconnect and resistor for integrated circuits

A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped conductive layer (24) having a conductivity of a first type. A oxide layer (26) is formed over the integrated circuit with a first opening (25) therethrough exposing a portion of the conductive layer (24). Using the oxide layer (26) as a mask, the exposed portion (25) of the conductive layer (24) is then implanted with a dopant of a second conductivity type to form a junction (27) between the exposed portion and the portion covered by the mask. A oxide region (30) is then formed on a portion of the oxide layer (26) in the first opening (25), over the junction (27) and over a portion of the exposed conductive layer (24) adjacent to the junction (27). A silicide (36) is formed over the exposed portion of the conductive layer (24).