MULTIPLE LAYER COLLECTOR STRUCTURE FOR BIPOLAR TRANSISTORS
Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | HILL, DARRELL G LIU, WILLIAM UEIUNG |
| description | Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0520482A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0520482A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0520482A33</originalsourceid><addsrcrecordid>eNrjZLDyDfUJ8QzwcVXwcYx0DVJw9vfxcXUO8Q9SCA4JCnUOCQ1yVXAD8pw8A_x9HIMUQoIc_YI9g4EKgnkYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSbxrgIGpkYGJhZGjsTERSgCoRCk0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTIPLE LAYER COLLECTOR STRUCTURE FOR BIPOLAR TRANSISTORS</title><source>esp@cenet</source><creator>HILL, DARRELL G ; LIU, WILLIAM UEIUNG</creator><creatorcontrib>HILL, DARRELL G ; LIU, WILLIAM UEIUNG</creatorcontrib><description>Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940622&DB=EPODOC&CC=EP&NR=0520482A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940622&DB=EPODOC&CC=EP&NR=0520482A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HILL, DARRELL G</creatorcontrib><creatorcontrib>LIU, WILLIAM UEIUNG</creatorcontrib><title>MULTIPLE LAYER COLLECTOR STRUCTURE FOR BIPOLAR TRANSISTORS</title><description>Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDyDfUJ8QzwcVXwcYx0DVJw9vfxcXUO8Q9SCA4JCnUOCQ1yVXAD8pw8A_x9HIMUQoIc_YI9g4EKgnkYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSbxrgIGpkYGJhZGjsTERSgCoRCk0</recordid><startdate>19940622</startdate><enddate>19940622</enddate><creator>HILL, DARRELL G</creator><creator>LIU, WILLIAM UEIUNG</creator><scope>EVB</scope></search><sort><creationdate>19940622</creationdate><title>MULTIPLE LAYER COLLECTOR STRUCTURE FOR BIPOLAR TRANSISTORS</title><author>HILL, DARRELL G ; LIU, WILLIAM UEIUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0520482A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HILL, DARRELL G</creatorcontrib><creatorcontrib>LIU, WILLIAM UEIUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HILL, DARRELL G</au><au>LIU, WILLIAM UEIUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTIPLE LAYER COLLECTOR STRUCTURE FOR BIPOLAR TRANSISTORS</title><date>1994-06-22</date><risdate>1994</risdate><abstract>Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_EP0520482A3 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | MULTIPLE LAYER COLLECTOR STRUCTURE FOR BIPOLAR TRANSISTORS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T11%3A55%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HILL,%20DARRELL%20G&rft.date=1994-06-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0520482A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |