Digital synchronizing arrangement using a tuned tapped delay line

The synchronizing arrangement synchronizes a digital data signal (Din) applied to its data input terminal (Din) with a local clock (CKin) applied to its clock input (CKin). It includes a tuned tapped delay line (TDL) where the local clock (CKin) is delayed, a sampling circuit (DR2,.,DR4) where the digital data signal is sampled using a number of delayed clock signals, a first processing circuit (P) where the middle of a 0 1 0 pattern included in the signal is determined, a second processing circuit P2 where the variation in time of that middle is determined and an output circuit where based on the mentioned middle and variation, one of the delayed clock signals is selected to read the digital data signal. The tuned tapped delay line includes a tapped delay line and a feedback circuit at two inputs of which the input of the tuned tapped delay line and its 90 degrees tap are applied. The output of the feedback circuit is connected to a control input of the tapped delay line.