Bipolar element bifet array decoder

A decoder implemented using bifet technology to exhibit high performance, high density, and low power dissipation. The decoder has multiple input lines for conducting signals at ECL-compatible voltage levels and an output line for conducting signals at CMOS-compatible voltage levels. The output line is enabled in response to a predetermined combination of ECL-compatible voltage level signals on said input lines. The decoder comprises a gate for generating an OR output at ECL-compatible voltage levels according to the input line signals. An inverter is coupled to the OR gate for inverting and amplifying the OR output to produce an inverted output at CMOS voltage levels. A word line driver is coupled to an output of the inverter for isolating and driving the output line according to the inverted output. Finally, power saving means are coupled to the inverter for minimizing power dissipation in the decoder.