Process for producing a printed wiring board

Process for producing a printed wiring board

A process for the production of a printed wiring board which comprises preparing a copper-clad laminate (1a,1b) having a through-hole (10) formed by drilling; providing a first resist pattern (21) on the surface of the copper-clad laminate (1a,1b) so as to cover a portion (16) to be formed as a cond...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SHIMODA, HIDETOSHI, UCHIDA, HIROYUKI, TAKAHASHI, TOSHIO, KOBAYASHI, TADASHI
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SHIMODA, HIDETOSHI
UCHIDA, HIROYUKI
TAKAHASHI, TOSHIO
KOBAYASHI, TADASHI
description A process for the production of a printed wiring board which comprises preparing a copper-clad laminate (1a,1b) having a through-hole (10) formed by drilling; providing a first resist pattern (21) on the surface of the copper-clad laminate (1a,1b) so as to cover a portion (16) to be formed as a conductor pattern; etching the copper-clad laminate (1a,1b) removing the first resist pattern (21); subjecting the whole laminate to an electroless copper plating (3); laminating a dry film resist (4) on the copper-clad laminate (1a,1b); exposing and developing the dry film resist (4) to form a second resist pattern (41) in such a manner that the through-hole (10) and a portion to be plated are exposed; subjecting the exposed portions to an electrolytic copper plating (5); removing the second resist pattern (41); and removing the exposed electroless copper plating (3) through etching.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0472158A2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0472158A2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0472158A23</originalsourceid><addsrcrecordid>eNrjZNAJKMpPTi0uVkjLL1IoKMpPKU3OzEtXSASyM_NKUlMUyjOLQAJJ-YlFKTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JN41wMDE3MjQ1MLRyJgIJQA91ClT</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Process for producing a printed wiring board</title><source>esp@cenet</source><creator>SHIMODA, HIDETOSHI ; UCHIDA, HIROYUKI ; TAKAHASHI, TOSHIO ; KOBAYASHI, TADASHI</creator><creatorcontrib>SHIMODA, HIDETOSHI ; UCHIDA, HIROYUKI ; TAKAHASHI, TOSHIO ; KOBAYASHI, TADASHI</creatorcontrib><description>A process for the production of a printed wiring board which comprises preparing a copper-clad laminate (1a,1b) having a through-hole (10) formed by drilling; providing a first resist pattern (21) on the surface of the copper-clad laminate (1a,1b) so as to cover a portion (16) to be formed as a conductor pattern; etching the copper-clad laminate (1a,1b) removing the first resist pattern (21); subjecting the whole laminate to an electroless copper plating (3); laminating a dry film resist (4) on the copper-clad laminate (1a,1b); exposing and developing the dry film resist (4) to form a second resist pattern (41) in such a manner that the through-hole (10) and a portion to be plated are exposed; subjecting the exposed portions to an electrolytic copper plating (5); removing the second resist pattern (41); and removing the exposed electroless copper plating (3) through etching.</description><language>eng ; fre ; ger</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920226&amp;DB=EPODOC&amp;CC=EP&amp;NR=0472158A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920226&amp;DB=EPODOC&amp;CC=EP&amp;NR=0472158A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIMODA, HIDETOSHI</creatorcontrib><creatorcontrib>UCHIDA, HIROYUKI</creatorcontrib><creatorcontrib>TAKAHASHI, TOSHIO</creatorcontrib><creatorcontrib>KOBAYASHI, TADASHI</creatorcontrib><title>Process for producing a printed wiring board</title><description>A process for the production of a printed wiring board which comprises preparing a copper-clad laminate (1a,1b) having a through-hole (10) formed by drilling; providing a first resist pattern (21) on the surface of the copper-clad laminate (1a,1b) so as to cover a portion (16) to be formed as a conductor pattern; etching the copper-clad laminate (1a,1b) removing the first resist pattern (21); subjecting the whole laminate to an electroless copper plating (3); laminating a dry film resist (4) on the copper-clad laminate (1a,1b); exposing and developing the dry film resist (4) to form a second resist pattern (41) in such a manner that the through-hole (10) and a portion to be plated are exposed; subjecting the exposed portions to an electrolytic copper plating (5); removing the second resist pattern (41); and removing the exposed electroless copper plating (3) through etching.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAJKMpPTi0uVkjLL1IoKMpPKU3OzEtXSASyM_NKUlMUyjOLQAJJ-YlFKTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JN41wMDE3MjQ1MLRyJgIJQA91ClT</recordid><startdate>19920226</startdate><enddate>19920226</enddate><creator>SHIMODA, HIDETOSHI</creator><creator>UCHIDA, HIROYUKI</creator><creator>TAKAHASHI, TOSHIO</creator><creator>KOBAYASHI, TADASHI</creator><scope>EVB</scope></search><sort><creationdate>19920226</creationdate><title>Process for producing a printed wiring board</title><author>SHIMODA, HIDETOSHI ; UCHIDA, HIROYUKI ; TAKAHASHI, TOSHIO ; KOBAYASHI, TADASHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0472158A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1992</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIMODA, HIDETOSHI</creatorcontrib><creatorcontrib>UCHIDA, HIROYUKI</creatorcontrib><creatorcontrib>TAKAHASHI, TOSHIO</creatorcontrib><creatorcontrib>KOBAYASHI, TADASHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIMODA, HIDETOSHI</au><au>UCHIDA, HIROYUKI</au><au>TAKAHASHI, TOSHIO</au><au>KOBAYASHI, TADASHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Process for producing a printed wiring board</title><date>1992-02-26</date><risdate>1992</risdate><abstract>A process for the production of a printed wiring board which comprises preparing a copper-clad laminate (1a,1b) having a through-hole (10) formed by drilling; providing a first resist pattern (21) on the surface of the copper-clad laminate (1a,1b) so as to cover a portion (16) to be formed as a conductor pattern; etching the copper-clad laminate (1a,1b) removing the first resist pattern (21); subjecting the whole laminate to an electroless copper plating (3); laminating a dry film resist (4) on the copper-clad laminate (1a,1b); exposing and developing the dry film resist (4) to form a second resist pattern (41) in such a manner that the through-hole (10) and a portion to be plated are exposed; subjecting the exposed portions to an electrolytic copper plating (5); removing the second resist pattern (41); and removing the exposed electroless copper plating (3) through etching.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP0472158A2
source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title Process for producing a printed wiring board
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T07%3A37%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHIMODA,%20HIDETOSHI&rft.date=1992-02-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0472158A2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true