Floating gate field effect transistor structure and method for manufacturing the same

A stacked floating gate field effect transistor (FET) structure for a UV EPROM or EEPROM array and method for making the same are disclosed in which a polysilicon floating gate layer (18) is formed on a silicon substrate (30), a layer of oxide is formed on the sidewalls (42) of the floating gate and then an oxide-nitride-oxide (ONO) composite layer (44) is formed overtop of the entire array substrate, including the floating gate (18) and the sidewall oxide (42). The ONO composite layer (44) and the sidewall oxide layers (42) act as an isolation dielectric between the floating gate (18) and a control gate (20) which is formed on top of the ONO layer (44).