A logic simulation using a hardware accelerator together with an automated error event isolation and trace facility

Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators (70, 200) operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators (70, 200) so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator (70, 200) state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator (70, 200) is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator (70, 200) is supplied to a software simulator for detailed error analysis and fault tracing. The hardware accelerator (70, 200) may then be restarted where it left off or with a different task. In this way, optimal utilization is made of expensive hardware accelerator (70, 200) resources while nonetheless providing error event isolation and the ability to generate detailed traces of simulated behavior.