Sequential prefetch method for 1, 2 or 3 word instructions

A sequential prefetch method is provided for a pipelined data processor (10) having a sequential instruction prefetch unit (IPU) (34). An instruction queue (50) in the IPU (34) is coupled to a pipelined instruction unit (32) and an instruction cache (14) of the data processor (10). A prefetch controller (56) in the IPU (34) keeps the instruction stream prefetched so that the instruction queue (50) may load any combination of one, two, or three word instructions into the pipelined instruction unit (32) every clock cycle. The pipelined instruction unit (32) receives instruction words from the instruction queue (50), and decodes the instruction for execution operations, and for the instruction length/pipeline movement. A queue filling method is provided for maintaining the requisite number of instruction words in the instruction queue (50) to avoid pipeline stalls. The queue filling method is based upon the movement of the instruction pipeline (32) attributable to the usage by an instruction sequencer (32) of the instruction words received from the instruction queue. (50)