Data processing system with direct memory access controller and method for varying communication bus masterchip in response to prioritized interrupt requests

A data processing sytem (10) having a direct memory access controller (DMAC) (12) which can be interrupted with a priortized signal to vary bus mastership of a communication bus (14) in the system. A prioritized interrupt signal is sent to a CPU (11) when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.