A memory module utilizing partially defective memory chips
A memory device which includes several partially defective memory chips and a control circuit (1) for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective m...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A memory device which includes several partially defective memory chips and a control circuit (1) for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled. The control circuit according to the invention can be implemented to control the chip driver circuit of a variety of different sizes of memory chips. For example, the control circuit can be implemented for controlling the chip driver circuit of a one-quarter size memory chip, a one-half size memory chip, a three-quarter size memory chip, or a full-size memory chip. |
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