HIGH STRENGTH LOW STRESS ENCAPSULATION OF INTERCONNECTED SEMICONDUCTOR DEVICES

HIGH STRENGTH LOW STRESS ENCAPSULATION OF INTERCONNECTED SEMICONDUCTOR DEVICES

A semiconductor packaging technique employing a high Young's modulus, localized, external connection to pad (2), bond immobilizing member (9), together with, as needed, a low Young's modulus environmental protection covering member (11). A chip (1) of Si or GaAs has an annulus (9) of high...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: NOYAN, ISMAIL C, KOVAC, CAROLINE A
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A semiconductor packaging technique employing a high Young's modulus, localized, external connection to pad (2), bond immobilizing member (9), together with, as needed, a low Young's modulus environmental protection covering member (11). A chip (1) of Si or GaAs has an annulus (9) of high Young's modulus epoxy over the line of external connections such as beam leads (3) or wire bonds (4) near the edge and a coating (11) of silicone over the entire chip surface including the annulus (9).