Synchronous bus

A high-speed synchronous bus is provided for a computer system that allows efficient communication among a plurality of processors or other data devices coupled to the bus. The bus provides systematic bus access, without arbitration, to data devices connected to the bus, and employs a central bus grant scheme for pre-allocated access to the bus by each data device. Data devices cannot seize or hold the bus. Means are provided for insuring that the bus is always in a read or write mode for a time which is long relative to the cycle time of the bus. Bus timing includes, for each bus frame, a number of time slots allocated to respective data devices. During a bus frame, access to memory is synchronized. According to another aspect of the invention, two clock signals are propagated in opposing directions on the bus to control similarly traveling data signals. Also included are means for achieving a fast bus cycle time, typically in the range of 20 - 60 nanoseconds per cycle, which is less than the cycle time of the computer system. A backplane is provided of a length which can be driven reliably at the cycle time of the bus, and which is modularly expandable