CROSSTALK-SHIELDED-BIT-LINE DRAM

This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit lines (e.g. BL2, BL2 min ) are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines (e.g. BL1, BL1 min and/or BL3, BL3 min ) as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines (BL1, BL2; BL1 min , BL2 min )associated with a common sense amplifier (10). One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.