Semiconductor memory with high cell density

A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, a storage capacitor (16) having a storage node (20) disposed within a given sidewall of the trench (24), a switching device (12) coupled to the storage capacitor (16) and having an elongated current carrying element (22) disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench (24) and a control element (14) disposed on the sidewall of the trench (24) between the storage capacitor (16) and the elongated current carrying element (22), and an electrically conductive line (28) disposed on the major surface of the semiconductor substrate (26) in a direction orthogonal to the longitudinal axis of the trench (24) and in contact with the control element (14) of the switching device (12). Furthermore, two complete memory cells (10A, 10B) are formed at each trench-word line intersection with one cell formed on each side of the trench (24) at each intersection.