Dielectrically isolated semiconductor device and method

Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced by etching recesses (14) in a (e.g.,N) single crystal semiconductor wafer (12), coating with a dielectric (21) and a thick polycrystalline semiconductor layer (24) to provide a support, and back lapping to expose dielectrically isolated N islands (22 min ) located between the original recesses (14). Depressions (55) are etched in the N islands (22 min ) filled with a more lightly doped (e.g., N) semiconductor (62). The structure is then planarized (e.g., by lapping and etching) to give isolated single crystal islands having a surrounding N periphery (58, 59) and an N central epi region (62 min ) of well controlled thickness and a smooth outer surface (67) suitable for device formation. Bipolar transistors of excellent properties are formed by providing a nested base and emitter within the central region. The surrounding N periphery (58, 59) automatically provides a buried layer (58) and buried layer contact (59).