Process for forming high-voltage and low-voltage CMOS transistors on a single integrated circuit chip

Process for forming high-voltage and low-voltage CMOS transistors on a single integrated circuit chip

A process for forming both low-voltage CMOS transistors and high-voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well (174,374) of each PMOS transistor and the n-type drain extension well (274) of each lightly-doped dr...

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Bibliographische Detailangaben
Hauptverfasser: PARRISH, JACK DUANA, SCHNABEL, DOUGLAS ROBERT, MANN, JONATHAN DOUGLAS, KOSIAK, WALTER KIRK, ROWLANDS, PAUL RUSSELL, III
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:A process for forming both low-voltage CMOS transistors and high-voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well (174,374) of each PMOS transistor and the n-type drain extension well (274) of each lightly-doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well (182) of each LDD PMOS transistor.