ECL EPROM with CMOS programming

The present invention provides an ECL EPROM circuit which uses a MOS memory cell (50). The invention includes a technique for programming the memory cell (50) using MOS voltage levels, and also includes circuitry for reading the memory cell (50) at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components (64, 66, 68, 70) for reading the cell, while the writing path contains MOS components (54, 56, 58, 60, 73) for programming and verifying the cell (50). The memory cell (50) itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element. The MOS memory element is coupled to the programming (writing) path, and the ECL pass element is coupled to the read path with a bipolar output transistor.