Modular expandable single stage digital ATM switching network for high speed packet-switched information transfer

A modularly expandable digital single-stage ATM (Asynchronous Transfer Mode) switching network for high-speed packet-switched information transfer, comprising a preprocessing module (VVM), in which arrangement preprocessing is only carried out with respect to the matrix column but not with respect to the matrix output and the number of expansion inputs and the number of first outputs of the preprocessing module is 1/L, namely N, of that of the expansion module, this module containing a single FIFO store (SP) which can simultaneously enter 2N packets and simultaneously read out N packets and in which arrangement, to avoid so-called overtaking by packets, the order in time of packets in each case arriving on one of the N first-input lines of a preprocessing module (VVM) is replaced case by case by a spatial order on the N first-output lines of the preprocessing module (VVM). An overhead information filter (KF) only processes a part of the overhead information of the data packets for switching the packets to the relevant switching module column. In addition, a further preprocessing module (VVM) and a final processing module (EVM), which carries out final switching to the matrix output, are provided per matrix column, in which arrangement the first outputs of these preprocessing modules (VVM) are connected to the relevant inputs of the final processing modules (EVM). The final processing modules (EVM) do not have any expansion inputs or expansion outputs. The overhead information filter (KF) of the final processing module (EVM) processes a different part of the overhead information for the final switching to a matrix output.