Semiconductor static memory device

A semiconductor memory device includes: a pair of bit lines (BL1,BL2); a memory cell(R1,R2,Q1 SIMILAR Q4) provided between the pair of bit lines, the bit lines having a potential difference therebetween when information stored in the memory cell is read out ; and a potential difference control unit (1,Q13), operatively connected to the pair of bit lines, for increasing the potential difference between the pair of bit lines up to a predetermined level in response to a first control signal ( phi 1), thereby realizing a high speed read operation and adapting the present device to a reliable discrimination of "good" or "no good" in a screening test.