Neuron architecture

Neuron architecture in which input analog data is applied in parallel to a plurality of neuron units (Fig. 2; Fig. 4 U1 to U5) in a time division manner. The analog input data is multiplied (3) by digital weight data which can be changed in accordance with the data of the interconnection between units. The product of the time division analog input data and the digital weight data are added in an integrator (4). While the sum of the products is output with regard to the present result, the previous sum of the product is output through a non-linear function forming means (6) simultaneously with the present data, thereby enabling operations for the sum of product in a neuron unit in an intermediate layer (e.g. U1, U2, U3) simultaneously with operations in a neuron unit in an output layer (e.g. U4, U5) and thereby providing outputs in a pipe-line manner. When a first neuron unit (e.g. U1) in a layer produces an output (y1) on an analog bus (A), a second neuron unit (e.g. U2) in the same layer is able to produce an output (y2) such that the outputs (y1, y2, y3) of the first layer are produced on the output analog bus (A) in a time division manner. An analog neuron unit or chip includes a plurality of operational amplifiers. The offset thereof is cancelled by offset cancelling means (8). The above analog neuron unit may be used to provide an intermediate layer and an output layer, so that a neuron system is provided which operates in the form of a layered structure (Fig. 4). One layer comprising a plurality of neuron units (U1, U2, U3) can be repeatedly used by feeding back the output of one layer to the input of another layer to form a neuron system with a layered structure.