PROCESS FOR INVESTIGATING THE LATCH-UP EXTENSION IN CMOS CIRCUITS

A knowledge of the latch-up extension in integrated CMOS circuits is of decisive importance for the microelectronic device development engineer in order to be able to reduce latch-up sensitivity in such circuits by a design change or technological measures. Since the known methods of investigating the latch-up extension have only a relatively low time resolution, it is proposed to trigger the latch-up periodically, to sample the intensity of the infrared radiation originating from the circuit consecutively at a plurality of measuring points covering the circuit in the form of a grid at a specified time tau after the occurrence of the trigger signal initiating the latch-up and to record a measured value representing the intensity I( tau ) as a function of the position in each case.