Local memory fast selecting apparatus

Local memory fast selection apparatus in a data processing system having a plurality of memory resources and addressing by logical/virtual addresses which are converted into physical addresses, comprising a memory management unit MMU (2) for converting a logical address in a physical address and for generating a destination code which identifies the memory resource, an auxiliary memory (16) having the same number of addressable locations of the MMU (2) and loaded together with the MMU (2), this last with a physical address corresponding to the logical address by which the MMU (2) is addressed and with a destination code, the auxiliary memory (16) with a bit decoded from said destination code for selecting a predetermined memory resource, the auxiliary memory (16) and the MMU (2) being read out together with the same logical address, so as to jointly obtain a physical address from the MMU (2) and a selection signal of the predetermined memory resource from the auxiliary memory (16), without any delay caused by decoding operations.