Processor simulation

The arrangement disclosed simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by using a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions. A method is used to determine at the time of a store to memory whether an instruction, data, or video, is being updated. If the memory location that is being updated contains an instruction, the simulator takes additional steps to guarnatee the correct execution of the modified instruction. If the simulator determines at the time of a store that the the memory location being modified is data, the simulator needs to take no additional steps.