PROGRAMMABLE LOGIC ARRAYS

Programmable logic arrays (PLAs) in the form of a matrix having each array column consisting of a plurality of FETs (Field Effective Transistors) in which cell arrays constituting each array column for producing logical product output signals are divided into a plurality of array blocks (11,13) so as to reduce the number of the FETs to be connected in series in each array block and to eventually reduce the series resistance of each of the array columns, and the output signals from each of the array blocks thus divided are applied to the input terminals of each logical circuit so as to reduce each combined logical product from each logical gate, thereby realizing high speed operation for the PLAs.