Mask generation circuit

A mask generator circuit for generating a bit mask sequence of 2 bits including a first logic circuit having a single level of combinational logic for receiving an N bit indication of the bit mask sequence and for providing an output of 2 plus 2 signals to a second logic circuit that includes 2 identical logical units of not more than 2 levels of combinational logic each connected in parallel and each unit including 2-1 repeating circuit sets. These units are connected to receive the signals from the first logic circuit and provide therefrom the bit mask sequence. A bit mask generator is provided that includes a first edge generator circuit and a second edge generator circuit where each of the edge generator circuits are provided N bit indications indicating the binary digital sequence transition point. The output of the edge generator are provided to a combinational logic circuit that combines these two edge bit mask sequences to provide the mask sequence.