CMOS off-chip driver circuit

A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor (32) arranged in series with a second or pull-up P-channel transistor (30) and a third P-channel transistor (36) connected from the common point (B) between the first and second transistors (32, 30) and the gate electrode of the first transistor (32). The first and second transistors (32, 30) are disposed between a data output terminal (24) and a first voltage source (28) having a supply voltage of a given magnitude, with the data output terminal (24) also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor (38), disposed in a common N-well (40) with the other P-channel transistors, is connected at its source to the first voltage source (28) and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.