Interruptible cache loading
A system for interrupting loading of data into a high speed memory device from main storage. A high speed cache is connected to main storage for storing at least a subset of the data residing therein and for accessing data from a processor. A buffering device is connected to main storage and to the...
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| Hauptverfasser: | , , |
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A system for interrupting loading of data into a high speed memory device from main storage. A high speed cache is connected to main storage for storing at least a subset of the data residing therein and for accessing data from a processor. A buffering device is connected to main storage and to the cache for buffering data to be loaded therein. The data buffer is adapted to receive data from main storage continuously and is adapted to transfer the data to the cache continuously unless the cache is being accessed by the processor. |
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