Fast C-MOS adder

Fast C-MOS adder

The elementary adder, as far as carry propagation is concerned, comprises two circuit branches: the first is an inverter (I1) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LICCIARDI, LUIGI, TORIELLI, ALESSANDRO
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:The elementary adder, as far as carry propagation is concerned, comprises two circuit branches: the first is an inverter (I1) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series circuit, two P-MOS (T3, T4) and two N-MOS (T5, T6) generating carry output CoutN complemented when the two operands have equal logic levels.