A non-inverting repeater circuit for use in semiconductor circuit interconnections

A semiconductor non-inverting repeater circuit utilizes a pair of current mirrors (P1, P2; N1, N2) operating in a balanced source/sink operation during non-input signal periods to provide quiescent biasing current to a pair of complementary bipolar output transistors (T1, T2). The bipolar output transistors are configured in a complementary emitter-follower arrangement to provide minimum delay. Finally, the circuit includes two diodes (D1, D2) and two capacitors (C1, C2) to supply a non-inverted input signal to the bipolar output transistors such that a non-inverted output signal is produced.