High density, high performance register file circuit

Register file circuit (10) includes an array of storage cells (20) arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch (24) has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch (24) applies its decoded output to a multiplexer (30) which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array (40). The output storage cell array (40) is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array (40) stores the data from the selected read lines out of the multiplexer (30). The multiplexer (30) propagates the data signals output from the read lines and performs the selection during the delay period between the master clock signal and the slave clock signal. Thus, the circuit makes use of the dead time between the master clock signal and the slave clock signal which was heretofore wasted, in performing the selection of the read lines for latching in the output storage cell array (40). The feature of connecting separate read lines to each respective storage cell in the array allows the independent accessing of different register rows in the register file circuit (10) for reading and writing, during the same logic cycle defined by the interval for the occurrence of both the master and the slave clock pulses.