POROUS CIRCUIT MACRO FOR SEMICONDUCTOR INTEGRATED CIRCUITS

A circuit macro (10) is provided for a VLSI circuit device having a semiconductor substrate and M1 and M2 metal layers defining a grid of M1 and M2 conductive lines extending in orthogonal directions. Numerous similar unit cells are arrayed side-by-side in rows extending in one direction and each unit cell spans an integral number of M1 conductive lines and an integral number of M2 conductive lines. The circuit device includes a plurality of circuit blocks (34,36), each including two of the rows of unit cells. A plurality of wiring bays (38) extend between adjacent circuit blocks, and each wiring bay includes a plurality of M1 conductive lines. The circuit macro includes a number of circuit blocks separated by wiring bays, and connections extend to unit cells of circuit blocks included in the macro. Both M1 and M2 conductive lines are used for connections in the macro, and additional M1 and M2 conductive lines, including M1 conductive lines in the wiring bays, extend uninterrupted across the macro providing a porous yet dense macro and facilitating macro placement and wiring.