FAULT TOLERANT COMPUTER ACHITECTURE

In a fault tolerant computer architecture in which a functional unit is duplicated and the signals in input/output to/from the two units, are compared each other by comparators to provide an error signal in case of different behaviour of the two units, resulting in differing input output signals to/from the two units, and in which the operation of both functional units is controlled by a first read only control memory or alternatively by a second read/write control memory, once it has been loaded with microprograms, under control of the first read only control memory, the correct behaviour of the comparators is tested in diagnostic mode, by having a functional unit operated under control of the first memory and the other functional unit operated under control of the second memory, so that the two units are controlled to perform differing functions which force the comparators to produce an error indication, missing which, the comparators operation is faulty.