CIRCUIT COMBINING FUNCTIONS OF CYCLIC REDUNDANCY CHECK CODE AND PSEUDO-RANDOM NUMBER GENERATORS

A circuit is disclosed which combines the functions of a cyclic redundancy check code (CRCC) generator and a pseudo-random number generator in such a way that common elements are shared rather than duplicated. A 16-stage shift register and two linear feedback paths are included for the CRCC and pseudo-random number generators. A control section of the circuit controls the mode of operation of the circuit according to the state of a mode control signal. A signal on a clear line resets the shift register or initializes it with a selected value depending on the state of the mode control signal. The mode control signal also controls the input of data on a data line and the output of generated CRC and pseudo-random access codes on output lines.