METHOD OF AND APPARATUS FOR PROCESSING DATA

A data processor of this invention specifies (16, 17) either of a predetermined maximum length of an address (a bits) and the length of an address less than the former length and at least one register (7) having the number or length of bits of the maximum address length or greater (r bits). The data processor reads out lower-order d bits of said at least one register (7) specified by a first instruction to perform arithmetic operations, and writes the arithmetic result into a register element contained in said at least one register (7). Moreover, the processor reads out bits from a register element contained in said at least one register (7) specified in a second instruction to generate an a-bit address, and reads out d bits from a storage device (5) in response to the thus-generated address to write the d bits into either the storage device (5) or said register element. Accordingly, since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address. Facilitating extension of the length of a storage address and assuring compatibility with conventional data processor.