LOGIC-CIRCUIT LAYOUT FOR LARGE-SCALE INTEGRATED CIRCUITS

LOGIC-CIRCUIT LAYOUT FOR LARGE-SCALE INTEGRATED CIRCUITS

A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.

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Bibliographische Detailangaben
Hauptverfasser: WILLIAMS, ROBERT RUSSELL, DUNHAM, BRADFORD, FITZGERALD, JOSEPH MICHAEL
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.