LOW ACTIVE-POWER ADDRESS BUFFER
A buffer circuit accepting TTL input levels and generating logic-level signals incorporates means to reduce the power consumption in the circuit in the active phase as well as the inactive phase, without imposing additional restrictions on the user.
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | A buffer circuit accepting TTL input levels and generating logic-level signals incorporates means to reduce the power consumption in the circuit in the active phase as well as the inactive phase, without imposing additional restrictions on the user. |
|---|