SYSTEM BUS MEANS FOR INTER-PROCESSOR COMMUNICATION

A system bus and bus interface apparatus for connecting components in a data processing system having a plurality of non-memory and memory components. The system bus has the following sets of lines; A first plurality of lines carries a plurality of codes specifying a plurality of memory operations involving communications between a non-memory component and a memory component and a single code specifying an interprocessor communication between two non-memory components. A second plurality of lines carries an address in a memory component when the code on the first plurality of lines specifies a memory operation and a target address, an interprocessor communication type, and in some cases, a message, when the code on the first plurality of lines specifies an interprocessor communication. A third plurality of lines carries signals indicating the status of a memory operation, a fourth plurality of lines carries signals indicating the status of an interprocessor communication, a fifth plurality of lines carries data in memory operations and in certain interprocessor communications, and a sixth plurality of lines determines which of the components presently has access to the bus. Memory communications may specify read and write operations, but interprocessor communications may specify only operations in which the source component provided data to the destination component.