PHASE-LOCKED LOOP FOR MFM DATA RECORDING

A phase-locked loop (PLL) for use in decoding MFM data recordings. The loop uses a counter to generate timing signals which divide bitcells into data and clock windows and which define times within these windows at which transitions in the MFM signal are expected to occur. Data and clock windows of differing relative size are readily accomodated. The PLL has two synchronization modes: one mode allows the PLL to take maximum advantage of both data and clock transitions which occur when reading actual data; a second mode is used during the synchronization period at the beginning of a data block and allows the PLL to lock quickly yet assure that it will lock to the bit frequency and not lock to harmonics or beat frequencies. A charge pump generates the PLL error signal by responding to pump-up and pump-down control signals which are set and cleared in response to the timing signals from the counter and in response to the detection of transitions in the input signal. While in data mode, a second counter is used to control the charge pump when a transition occurs after the time the transition is expected to occur. The charge storage circuit of the charge pump control over loop dynamics. The PLL includes a VCO with an automatic dynamic adjustment of the VCO's center frequency which is accomplished by adjusting the reverse bias voltage on a diode that functions as the timing capacitor for the VCO. This adjustment allows the PLL to make maximal use of the VCO's range.