DUAL RANK SAMPLE AND HOLD CIRCUIT AND METHOD

A dual rank sample and hold circuit and method, particularly applicable to deglitching the output of a digital-to-analog converter. One signal path is provided for coupling an input signal to the output of the sample and hold circuit to track the input signal during sampling. A second signal path is provided for coupling the input signal to a storage capacitor for charging or discharging the capacitor to the level of the input signal. In one embodiment the output is coupled simultaneously via the first signal path to theJnput signal and through a resistor to the storage capacitor/during a sampling phase, the capacitor being coupled to the input signal, and thereafter only to the capacitor during a hold phase, the capacitor being decoupled from the input signal. In another embodiment the output is coupled alternatively through the first signal path to the input signal during a sampling phase, the capacitor being coupled to the input signal, and thereafter to the capacitor during a hold phase, the capacitor being decoupled from the input signal. In application to a digital-to-analog converter sampling begins after the analog output signal settles and ends prior to the next conversion event, and hold lasts past the next conversion event to the next sample.