Pipelined processor having dual cache memories

A pipelined digital computer processor system (10,) is provided comprising an instruction prefetch unit (IPU, 2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, ) for storing frequently accessed data, and a tag store (82, 92,) for indicating which main memory locations are contained in the respective cache. The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache. The IPU does not write to either cache. Provision is made for clearing the caches on certain conditions when their contents become invalid.