SMALL AREA THIN FILM TRANSISTOR

@ A method of forming a non-coplanar surface (20,143) in an etchable layer (14,16,18,140) which may include sublayer (14,16,18). The method includes depositing a layer (100,142) of photoresist over the etchable layer (14,16,18,140) and forming a second non-coplanar surface (106,148) in said layer (100,142) of photoresist. Then the etchable layer (14,16,18;140) is exposed to an etch through the second non-coplanar surface (20,143) below the second non-coplanar surface (106,148) in the photoresist (100,142).This method is used to make high performance, small area, thin film transistors having a drain layer (14,74), an insulating layer, (16,76), and a source layer (18,78) through which such a non-coplanar surface (20,82) is formed. The insulating layer (16,76) is formed between the source and drain layers (18,78;14,74). A deposited semiconductor (24,86) overlies the non-coplanar surface (20,82) to form a current conduction channel (24,86) between the drain and source. A gate insulator (26,88) and gate electrode (28,90) overlies at least a portion of the deposited semiconductor (22,84) adjacent thereto.