Apparatus and method for synchronization of peripheral devices via bus cycle alteration in a microprocessor implemented data processing system

Synchronization of the operation of a peripheral (16) with that of a processor (12) in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. Logic circuit means (48, 62, 72) are provided for monitoring the condition of a peripheral's status bits (40, 42) and for preventing an appropriate processor control signal (80) from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest (16) is readily identified by providing unique memory mapped locations (30), one for each system peripheral, that are responsively connected (18, 58, 56) to the logic circuit means (48).