CASCODED BISTABLE CIRCUIT FOR LEVEL SENSITIVE SCAN DESIGN

The circuit for level sensitive scan design (LSSD) comprises an L1 bistable device (11), an L2 bistable device (11). one current source (25), a first current switch logic means (17, 18) responsive to a first clock signal for selectively transferring data in L1 device (10) to L2 device (11), and a se...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	LEININGER, JOEL CALVIN, DAVIS, JAMES WILLIAM, ROBBINS, GORDON JAY, MUNOZ-BUSTAMANTE, CARLOS
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES TESTING
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	The circuit for level sensitive scan design (LSSD) comprises an L1 bistable device (11), an L2 bistable device (11). one current source (25), a first current switch logic means (17, 18) responsive to a first clock signal for selectively transferring data in L1 device (10) to L2 device (11), and a second current switch logic means (15, 16) device to supply current serially through said current switch logic means (15, 16) and L1/L2 devices so as to maintain each in a latch condition.