ASSOCIATIVE PROCESSOR AND METHOD OF FAST MULTIPLICATION WITH SUCH A PROCESSOR

An associative processor is described wherein an array (100) of associative processing cells is configured to achieve variable length fast multiplication of numbers, such as binary two's complement numbers, under mask control. In a configuration suitable for signed multiplication the processing sequences in all cells are compatible, each to the other, whether the cells are at the edges or the middle of an array row, and regardless of the computational sequences required to be performed. An associative cell structure, includes an improved arithmetic logic unit having separate carry and borrow save paths which may be enabled and active simultaneously or alternately.