Binary logic structure employing programmable logic arrays for microword generation

The structure includes and encode programmable logic array (13) responsive to a first group of binary input signals (E) such as a system instruction for producing a smaller number of binary signals (K) which are encoded to identify different binary value combinations for the first group of binary input signals (E), and a decode programmable logic array (14) responsive to a second group of binary input signals (F) and to the encoded binary signals (K) produced by the encode programmable logic array (13) for producing binary output signals (M) representing logical functions of the input signals which can be used as microwords for controlling a system. The chip space occupied by the encode programmable logic array (13) is less than the additional chip space that would be required if the encode and decode programmable logic arrays (13, 14) were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups.