INTERLACED PROGRAMMABLE LOGIC ARRAY HAVING SHARED ELEMENTS

INTERLACED PROGRAMMABLE LOGIC ARRAY HAVING SHARED ELEMENTS

A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: WIEDMAN, FRANCIS WALTER, KALTER, HOWARD LEO
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits (40) during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval (D1) and to provide the Exclusive-NOR of sums of product terms or the sum of the Exclusive-NOR of product terms during the second time interval (D2).