Control unit connectable to a pair of memories having different speeds

1. A clocked central control unit (CCU) operating under the control of a program stored in a storage unit attached to the control unit via an address bus (16), a data bus (18) and a control bus (19), said control unit being a microprogrammed type of unit and including a permanent storage for storing the microcodes, means for generating a multi-bit machine control word whenever an instruction in the stored program is executed, and means for inhibiting the clock, characterized in that : said storage unit comprises : at least one high-speed storage (11) for storing the most frequently used program instructions and data, said storage having a first set of address positions, at least one low-speed storage (10) for storing less frequently used program instructions and data, and having a second set of address positions, both of said high-speed and low-speed storages being addressed by the address information on the address bus, and said control unit comprises : a storage user indicator (STUI) having several output lines (A, B, C) for identifying a user requesting a storage read or write operation, said means (51) for inhibiting the clock comprises : a first logic circuit (65) which receives : at least a first bit (73, 80) of the machine control word indicating that the operation being performed is a storage read or write operation, which bit causes a signal indicating that an operation involving either storage is in progress to be generated on a first output, at least a second bit (53) of the machine control word indicating that a storage read or write operation has been initiated, which second bit causes a signal (S STUI) activating at least one of the output lines of said storage user indicator to be generated on a second outout of said logic circuit, and a third bit of the machine control word indicating that the Storage Busy condition does not result from a storage read or write operation, which third bit causes a signal (RST STUI) deactivating the output lines of said storage user indicator to be generated on a third output line of said logic circuit, a second logic circuit (66) which receives the signals on the output lines of the storage user indicator and generates a Storage Busy signal (STG BSY, 82) as long as completion of the storage read or write operation has not been signaled or as long as the output lines of said storage user indicator have not been deactivated, a third logic circuit (AND 79) which receives as inputs the first output from said firs