TWO STATE MEMORY CELL

A two state memory cell includes a bipolar transistor (11) and a tunnel diode (16) shunted across the base-collector junction thereof. A constant operating current is established through the transistor (11) and the tunnel diode (16). The voltage across the tunnel diode (16) may thus be maintained at one of two stable levels, while the bipolar transistor (11) is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell.Since the transistor (11) is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode (16) is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced. The tunnel diode/bipolar transistor combination may be formed on a semiconductor substrate as an integrated structure, thereby providing a high density memory cell.