DEVICE INTERFACING A MICROPROCESSOR BUS AND A SYNCHRONOUS PERIPHERY OF SENSORS AND DRIVERS

This device basically consists of a random access memory performing as an 'image' of the periphery conditions, and of the circuits controlling the addressing, the reading and the writing in the memory; said circuits permit either the access to the memory by the processor or the synchronous reading or writing of a plurality of sample frames directed to or coming from the periphery. The memory is organized in blocks of as many rows as are the samples in each frame; each block is associated with either sensors or drivers, and the processor can have access for the reading or writing to any row in each block, while the access for the synchronous reading or writing is possible only to the rows of the blocks associated with drivers or sensors, respectively.