METHOD AND APPARATUS FOR CONNECTING SEVERAL CENTRAL PROCESSORS TO DATA STORAGE DEVICES VIA ONE OR OTHER OF AT LEAST TWO PERIPHERAL PROCESSORS

1. A method for connecting a plurality of central processors (CPU I ...IV) to a plurality of data storage devices (DS) by means of at least one of two peripheral processors (5, 6) employing both a switching multiplexer (MCS) which is arranged between the respective peripheral processor (5 or 6) and its respectively assigned central processors (CPU I, CPU III or CPU II, CPU IV), and also individual address buffer stores (SB) which are respectively inserted at the in-/output intersection between the in-/output processor (IOP I...IV) of the respective central processor (CPU I...IV) and the assigned peripheral processor (5, 6), wherein an in-/output operation, which is started by one of the central processor (CPU I...IV), commences with the transmission and intermediate storage of a selection address (ADR), respectively assigned to one of the data storage devices (DS), in the address buffer store (SB), characterized in that following the transmission and storage of the selection address (ADR) the performance of the first command of the in-/output operation is temporarily interrupted for the purpose of a later continuation, and that if there is no hindrance of the separate peripheral processor (5 or 6) the intermediately stored selection address (ADR) is used in order to carry out cyclic-periodical addressing of the date storage device (DS) and to continue the temporarily interrupted in/ouptut operation by repeating the performance of the first command after the achieved selection.